1. Field of the Invention
The present invention relates to a method of making a novel Gallium Arsenide (GaAs) power semiconductor device and, and in more particular to a method of making a GaAs power metal-semiconductor field effect transistor operating at a low drain voltage for a digital hand-held phone.
2. Description of the Prior Art
In recent years, digital hand-held phone is on a minimizing trend in its size and weight. The volume and weight of a battery account for much of the weight in such a digital hand-held phone. The supply voltage of the battery also is increased in proportion to volume and weight of the battery. Advanced high performance hand-held phones require highly efficient medium-power transistors with a low operation voltage since the total size and weight of the phone can be drastically reduced as the number of battery cells decreases. Recent advances in material preparation and device fabrication techniques have resulted in L-band GaAs power FET's operating at low drain voltages of 3.0-3.5 V with respectable output power and efficiencies, but there has been no disclosure on the linearity performance.
In order to obtain a high efficiency at low biases of 3.0-3.5 V in a power semiconductor device, both a low knee voltage and a high gate-to-drain breakdown voltage in a power amplifying device are required. The low knee voltage entails a wide range of voltage swings of the RF output signal, which attributes to high power added efficiency(PAE) with high output power. In order to use power FET's for digital hand held phones, linearity performance should be high enough to reduce third-order inter-modulation, the magnitude of which is dependent upon the DC characteristics, namely transconductance variation with gate bias. At this point, an optimization of channel structure in the MESFET is essentially needed in developing low-voltage operation power MESFET with high PAE.
In order to develop a power semiconductor device having high output power and high PAE even at a low voltage, it is necessary to meet the following conditions:
low knee voltage PA1 high breakdown voltage PA1 high transconductance and low output conductance PA1 uniform transconductance in accordance with gate voltage PA1 low capacitance
However, the above mentioned conditions are contrary to each other in accordance with a channel structure of the device and a concentration profile thereof. For example, to obtain a low knee voltage in the device, if the distance between the source and gate and the distance between the gate and drain are reduced, the breakdown voltage characteristic of the device will be badly lowered. If the doping concentration of impurity ions is quantitatively increased in the channel of the device to obtain a high transconductance thereof, the breakdown voltage will be lowered. Therefore, it is important to optimize the above conditions in accordance with characteristics needed for a power semiconductor device.
Referring to FIG. 1, a conventional GaAs power semiconductor device has an undoped GaAs buffer layer 10 and a GaAs channel layer 20 which are sequentially formed on a semi-insulating GaAs substrate 70, a source electrode 40 and a drain electrode 60 which are formed on the channel layer 20 and electrically isolated by a passivation layer 30, and a gate electrode 50 which is formed in a recess portion formed by recess-etching the channel layer 20 between the source and drain electrodes. When the power semiconductor device is supplied with a source voltage, parasitic carriers are usually produced in the interface between the substrate 70 and the GaAs buffer layer 10. The parasitic carriers are introduced to the channel layer 20 through the GaAs buffer layer 10 during operation of the device. As a result, since a leakage current path is formed between the substrate and the channel layer, a leakage current and an output conductance are largely increased. As described above, in a case where a power semiconductor device has a high output conductance, it requires a relatively high source voltage for normal operation. If a power semiconductor device requires a high source voltage for normal operation, such power semiconductor devices can not be applied to a small digital hand-held phone.
FIG. 2 is a view showing current-voltage characteristics of a power semiconductor device which has the same construction to that of FIG. 1 and which has gate length of 0.8 mm and gate width of 150 mm. In FIG. 2, a knee voltage of the device is an intersection of dotted lines S.sub.A and D.sub.V representing a saturation current and a low drain voltage, respectively, and an output conductance is a gradient of current-voltage in a saturation current region. It can be seen from FIG. 2 that the knee voltage is approximately 1.7 V and the gradient of the output conductance is diagonally sloped.
In addition, in the efforts to realize high performance hand-held phone, there has been, based on electronic device innovation and specifically on submicron technology, a surge in the development of microstructure devices that take advantage of the high speed property of electrons in GaAs. A number of transistor types have been built. The most commercially successful of these devices is the MESFET--both the depletion mode (or D-MESFET) and enhancement mode (or E-MESFET) types. Under the gate of a D-MESFET is a normally-on region depleted of electrons which allows current to pass between the source and drain of the transistor. This region is doped to be n-type. When a negative voltage is applied, the width of the depletion region increases, the channel width through which the current flows decreases and the current flow is eventually pinched off. In an E-MESFET, the region under the gate is doped so that the channel is normally pinched off. Thus, small positive gate bias voltage must be applied for current to flow between the source and drain.
To meet the demands of high speed and integration density, the MESFET needs continual improvement. Potential improvements include shortening of the gate length, reducing the series resistance between the source and gate, decreasing the parasitic capacitance, especially the gate-source and gate-drain overlap capacitances, rendering the source/drain junction depths small and providing contact metallurgy which has a low resistivity and high thermal stability and compatible with shallow junction.
In this connection, the publication by K. Ueno et al entitled "High Transconductance GaAs MESFET with Reduced Short Channel Effect Characteristics" IEDM 85, pages 82-85 (1985) describes a GaAs MESFET, wherein the gate formed by etching a WSi.sub.x film. This publication discloses reducing short channel effect by employing a highly doped channel layer grown by molecular beam epitaxy and minimizing parasitic capacitance by utilizing oxide sidewall spacers between the gate and source/drain. Ueno et al uses a hot gate process in which the gate is formed first, followed by the formation of the source/drain. The basic disadvantage of the hot gate process is that the gate metal has a high resistivity which is not desirable for interconnection purposes. Also, the hot gate process does not permit threshold voltage trimming late in the device fabrication. After forming the gate by ion-milling planarization process, source/drain ohmic contacts are formed by AuGe/Ni deposition and sintering. The basic shortcoming of this disclosure is that it is unsuitably for forming submicron sized MESFET owing to significant (as much as 0.5 micron) lateral migration at high temperature of the gold in the AuGe/Ni metallurgy used for source/drain contacts causing electrical shorting. Also, the vertical transport of the gold precludes use of this process for forming shallow junction devices. Importantly, this process is limited to fabrication of a MESFET having a gate width dictated by resolution limit of lithography.
In order to overcome these problems, it has been proposed that a conventional MESFET structure be is provided with a gate which is of submicron length, symmetrical, planar and self-aligned to the source/drain via submicron-wide insulator spacers. Importantly, the gate does not overlap the source/drain, thereby eliminating the gate to source/drain overlap capacitance and increasing the device speed. The provision of the sidewall spacers minimizes device punch-through and short channel effects and permits good control of the device channel length and threshold voltage. Since the source/drain are placed extremely close to the gate, the source-gate series resistance is minimized, contributing to the device speed.
However, even in the above described MESFET structure, since parasitic carriers occurring in the semi-insulating GaAs substrate are introduced into the channel layer during operation of the device, a leakage current path is formed between the substrate and the channel layer. As a result, a leakage current and an output conductance are largely increased and thus the MESFET requires a relatively high source voltage for normal operation thereof.